Digital filters play a significant role in many signal processing applications. Every communication system and DSP (Digital Signal Processing) must have a Finite Impulse Response (FIR) filter. Two important components of filter architecture are the multiplier and adder. Digital circuits can be designed with a number of adders and multipliers, but an effective adder and multiplier design is required to create an efficient filter. While developing the digital Very Large Scale Integration (VLSI) circuits, an adder is one of the fundamental computational circuit. The concept behind Approximate Adders (AAs) is to improve the design metrics of the adders. The field of high-speed error-tolerant circuits with approximation computation has grown significantly due to the development of high-speed multimedia applications. Although these programs perform exceptionally well, accuracy is compromised. Their techniques additionally minimize system architecture complexity, delay, and power consumption. A proposal to improve the design metrics of an adder is called an approximate adder (AA). Multipliers are essential because they speed up the execution of intricate arithmetic procedures involving large numbers. The difficulty of today's world is that a multiplier allows to complete an operation in a single step quickly rather than to execute several addition or subtraction operations. The design and implementation of low power efficient FIR filter architectures using approximate adders and multipliers is presented in this work. A simple and fast approximation adder is proposed for approximate multiplier architectures. Area, delay, and power are used to evaluate the FIR filter's performance.