: The multiplier is a critical component in digital signal processing; for example the traditional array multiplier, MCM multiplier, DADDA Multiplier, its provides a fast and reliable technique, but it consumes a significant amount of area and power in all digital signal processing applications. This study of this work is a Multi-Band Transmitter digital signal processing application will have multiple baseband signal creation, FIR filter, multipliers. In Multi-Band Transmitter, the multiplier acquire huge importance to provide performance of area and power delay product, however the standard multiplier design takes up a lot of area and consumes a lot of power. Thus, this proposed work was introduced a Truncated Multipliers, rather than conventional multipliers, and its proposed for the design of the multi-band transmitter. A reconfigurable carrier aggregation transmitter with four and eight band bandwidths is also shown in this work, which employs several baseband signals shifted to a separate digital domain intermediate frequency (IF). 5G application of Carrier aggregation, for example, makes advantage of the reconfigurability of carrier spacing and the number of simultaneous carrier transmissions. Finally, this work has been created in Verilog HDL and synthesized on a Xilinx Vivado Zynq-7000 FPGA ZYNQ-7 ZC702, and all parameters in terms of area, delay and power have been compared.