Optimization of power consumption in any System on Chip is one of the most essential requirements for applications like wireless sensor networks. Voltage level converters perform this conversion while interfacing the devices with various voltage domains. With buffers, Level Up converters can be implemented without any overhead. This research proposes buffer architecture to realize Voltage Level Converter. The proposed Voltage Level Converter uses an effective Transmission Gate, Positive Metal Oxide Field Effect Transistor, and Negative Metal Oxide Field Effect Transistor to improve the efficiency of the Level Voltage Converter. The performance of the proposed LC architecture is verified by implementing it in the Spectre circuit simulator. The proposed architecture, while implemented on 90nm CMOS Technology, gives the result of voltage conversion from 650 mV, 570 mV, and 540 mV to 1.85 V by the architectures. Architecture has an improved propagation delay of 36 %, 34 %, and 38 % to the Basic Level Converter. Thus, the proposed architecture is Timetime- efficient and energy-efficient.